DAMP 2006

Source: http://glew.org/damp2006/cfp.txt

Workshop on         Declarative Programming Languages for Multicore Architectures Charleston, SC, USA 15 Janurary 2006 (informally colocated with POPL 2006)

Many chip manufactures are turning to multi-core processors rather than frequency increases in a single core as a way to get increasing performance in their desktop, enterprise, and mobile processors. This endeavour is not likely to succeed long term if mainstream applications cannot be parallelised to take advantage of 10s and eventually 100s of hardware treads. Parallelising programs is a difficult problem. User specification of parallelism is fraught with pitfalls such as race conditions, anticipated interactions between threads, difficult debugging models, and poorly understood performance consequencies. Automatic parallelisation of imperative langauges is difficult due to dependencies and aliasing.

Functional and logic programming languages, especially referentially-transparent ones, have many fewer and more transparent dependencies and aliasing. Therefore such langauges are much easier to extract parallelism from. Moreover, the advanced type systems and strong semantic foundations of these languages make correctness easier to achieve.

This workshop is an informal one-day event seeking to explore the leading role declarative programming languages might take in programming multi-core architectures. It seeks to gather together the research of the last two decades on parallelising declarative programming languages, examine what has changed from parallel machines to multicore chips, and set research directions for the coming decade.

Specific topics include, but are not limited to:

future multicore applications programs aliasing, effects, and nonpure features logic programs and logic programs declarative programming parallelisation
 * suitability of functional and logic programming languages to
 * extraction of parallelism from functional and logic programs
 * ways of specifying or hinting at parallelism in functional and logic
 * type systems for accurately knowing or limiting dependencies,
 * ways of specifying or hinting at data placement in functional and
 * implementation techniques to support parallelisation of functional
 * experiences of and challengers arising from making practical

Organisers:

Neal Glew Intel Corporation, Santa Clara, CA, USA neal.glew@intel.com

Leaf Petersen Anwar Ghuloum Jesse Fang

Sponsor:

Intel's Programming Systems Lab